1. "Optimizing DSP Flow Graphs via Schedule-Based Multi-Dimensional Retiming," (with E. H.-M. Sha and S. C. Bass) in theIEEE Transactions on Signal Processing, January 1996, pp. 150-155.

2. "Synchronous Circuit Optimization via Multi-Dimensional Retiming," (with E. H.-M. Sha) in the IEEE Transactions on Circuits and Systems vol. II - Analog and Signal Processing, vol. 43, n. 7, July 1996, pp. 507-519.

3. "Achieving Full Parallelism using Multi-Dimensional Retiming," (with E. H.-M. Sha) in the IEEE Transactions on Parallel and Distributed Systems, vol. 7, no. 11, November 1996, pp. 1150-1163.

4. "Optimal Data Scheduling for Uniform Multi-Dimensional Applications," (with E. H.-M. Sha and J. Q. Wang) in the IEEE Transactions on Computers, vol. 45, no. 12, December 1996, pp. 1439-1444.

5. "Multi-Dimensional Interleaving for Synchronous Circuit Design Optimization," (with E. H.-M. Sha and L.-F. Chao) in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, February 1997, Vol. 16, n. 2, pp. 146-159.

6. "Communication Sensitive Loop Scheduling for DSP Applications," (with E. H.-M. Sha and S. Tongsima) in the IEEE Transactions on Signal Processing, May 1997, Vol. 45, n. 5, pp. 1309-1322.

7. "Minimization of Memory Access Overhead for Multi-Dimensional DSP Applications via Multi-Level Partitioning and Scheduling," (with E. H.-M. Sha and J. Q. Wang) in the IEEE Transactions on Circuits and Systems vol. II - Analog and Signal Processing, September 1997, Vol. 44, n. 9, pp. 741-753.

8. "Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling," (with S. Tongsima, C. Chantrapornchai and E. H.-M. Sha) in the Journal of VLSI Signal Processing (invited paper), Volume 18, pp. 111-123.

9. "Scheduling of Uniform Multi-Dimensional Systems under Resource Constraints," (with E. H.-M. Sha) in the IEEE Transactions on VLSI Systems, December 1998, Volume 6, Number 4, pages 719-730.

10. "Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops," (with S. Tongsima, C. Chantrapornchai and E. H.-M. Sha) in the IASTED International Journal of Parallel and Distributed Systems and Networks, Volume 1, Number 4, pp. 204-211.

11. "Probabilistic Loop Scheduling for Applications with Uncertain Execution Time," (with S. Tongsima, C. Chantrapornchai, D. Surma and E. H.-M. Sha) in the IEEE Transactions on Computers, January 2000, Volume 49, Number 1, pp. 65-80.

12. "Efficient Polynomial-Time Nested Loop Fusion with Full Parallelism," (with T. W. O'Neil and E. H.-M. Sha) in the International Journal of Computers and Their Applications, March 2003, Volume 10, Number 1, pp. 9-24.

13. "Communication Scheduling with Re-routing based on Static and Hybrid Techniques," (with D. Surma and E. H.-M. Sha) in the Journal on Circuits, Systems and Computers, October 2004, Volume 13, Number 5, pp. 1039-1064.

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