CMPS 3023: Logic Design

Spring semester 2016

Instructor: Dr. Nelson L. Passos
Office: Bolin Science Hall 126B
Office phone: 397-4129
E-mail: nelson.passos@mwsu.edu
Webpage: cs.mwsu.edu/~passos
Office Hours: M    1:00 - 5:00 pm
  W    8:00 - 11:00 am
  TR  9:30 - 11:00 am
Class Hours: TR   12:30 - BO 127

Course Description:

Study of topics related to the design of modern microprocessors, including Boolean algebra, logic gates, design simplification techniques, memory design, programmable control units, and use of hardware description languages.

Text book:

Digital Design and Computer Architecture, by David Harris and Sarah Harris.

Lecture Notes:

CMPS 3023 Part 1

CMPS 3023 Part 2

Tools:

Quartus Web Edition Software

Download and installation instructions, read before downloading

Quartus - first time user instructions

Simulation instructions

 

Tentative Agenda:

January        February            March        April            May                                                                          Grading

January


Jan

19-

Introduction

Jan

21-

Binary numbers and data representation - a review

Jan

26-

Floating point

Jan

28-

Transistors and logic circuits


February


Feb

2-

Switching functions (AND, OR, NOT, NAND, NOR)

Feb

4-

Sum of products/product of sums

 

 

Assignment # 1

Feb

9-

Boolean algebra

Feb

11-

Logic to gates

 

 

Assignment # 2

Feb

16-

Donít cares

Feb

18-

Karnaugh maps

 

 

Assignment # 3

Feb

23-

Multiplexers/ Decoders

Feb

25-

HDL


March


Mar

1-

Timing

Mar

3-

Test # 1

Mar

8-

Sequential circuits

Mar

10-

Flip-flops

 

 

Assignment # 4

Mar

15-

Sequential  logic design

Mar

17-

Finite state machine

 

 

Assignment # 5

 

 

Project assignment

Mar

22

Spring Break

Mar

24

Spring Break

Mar

28

Easter Holiday

Mar

29

Easter Holiday

Mar

31-

Sequential  logic design


April


Apr

5-

Finite state machine

Apr

7-

FSM design

 

 

Assignment # 5

Apr

12-

Mealy and Moore machines

Apr

14-

Simplifying FSMs

 

 

Assignment # 6

Apr

19-

FF timing considerations

Apr

21-

Clock skew

Apr

26-

Parallelism

Apr

28-

Test # 2


May


May

3-

HDL sequential circuits

May

5-

Memory

May

12-

Finals (Thursday, 10:30 am)


Grading


 

Tests: 20 % (each)
Final Exam: 20 %
Assignments: 20 %
Project: 15 %
Class Participation:5 %
 


E-mail address:

nelson.passos@mwsu.edu

Back to Dr. Passos Home Page