"Improving Nested Loops' ILP on a Parallel ASIC Design"

(by R. P. Light, W. Maxfield, B. Reed, N. L. Passos, and E. H.-M. Sha) in the Proceedings of the 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, NV, August, 2000, pp. 105-110.

 

ABSTRACT

  Multi-dimensional applications such as satellite image processing, fluid mechanics, and medical imaging, require high computer performance. VLSI implementation of parallel Application Specific Integrated Circuits (ASICs) with limited number of processing units are commonly used to improve the performance of such computation-intensive applications. The critical sections of such applications consist of nested loops with the possibility of embedded conditional branch instructions. Branch predication techniques utilize predicate registers to control the validity of speculatively computed results. The use of such registers is a significant factor in the performance gain achievable by the overlap of successive iterations of a loop. This paper shows a process of dimensioning and scheduling those registers while scheduling the operations of the loop in a constrained parallel resource environment.

 

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